The invention relates to technology for implementing electronic design automation tools, and in particular, tools for performing latch-up check operations for design rule checks (DRCs) in an integrated circuit (“IC”) design.
An IC is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
Once the layout is finished, it is verified to make sure it satisfies the design rules, which are typically provided by the foundry that is to manufacture the IC device. This verification process is called Design Rule Check (DRC). The design rules are a set of rules regarding minimum distances, sizes, enclosure criteria, among other constraints for implementing the layout. The rules have to be observed in order to maximize chances of a successful fabrication of the integrated circuit.
Types of errors that are intended to be avoided by performing DRC include unwanted parasitic effects such as latch-up. To illustrate, consider the layout geometry shown in FIG. 1, which can be called an “nwell”. The nwell may include or be associated with arbitrary shapes. Inside the nwell are two geometries, one of which is called the n-tap or S and the other is the p-tap or D. The n-tap is marked as a circle and the p-tap is marked as a square.
To perform a latchup check, one of the rules that is measured is the distance between the n-tap to the p-tap inside the nwell. This check does not necessarily measure the most direct distance between them, but will measure the distance within the nwell between the two shapes.
One current approach to perform this type of latchup check is implemented as a sequence of sizing and AND operations. Essentially, an area is defined over a portion of the nwell and an AND operations is performed. The process then takes another area and performed another AND operation. This is a sequence that repeats itself as a series of such size/AND operations. The last step of the process is to identify areas in the nwell that are not appropriately covered by the analyzed areas, which are marked with an error if not within a suitable distance.
A drawback of this approach is that if there are two nwells that are adjacent to each other, then a large size may be drawn that overlaps portions of both nwells. Because of this, the size is limited by a minimum spacing between two nwells, so the process cannot use excessively large steps for the analysis, which could reduce efficiently of the process. Another problem that could result from not being able to use large steps is that there may exist some inaccuracy as a result.
Therefore, there is a need for an improved approach to implement latchup checks which are more efficient and accurate. Some embodiments of the present invention provides an efficient approach for performing latchup checks for an IC design. In one embodiment, partitioning is used to create separate sections of the geometry to analyze. The data is then checked by performing graph manipulations.